Conventional high-speed current-steering logic (HCSL) drivers can steer a constant current (e.g., 15 mA) between true and complementary outputs of a differential pair. As shown by the HCSL driver/receiver circuit 10a of FIG. 1A, traditional HCSL “end” termination uses a 50Ω resistor (RT) to ground at the end of each differential printed circuit board (PCB) trace. In contrast, the HCSL driver/receiver circuit 10b of FIG. 1B illustrates a type of “source” termination, which places the 50Ω resistors (RT) to ground nearer the HCSL driver (i.e., the drive “source”). As will be understood by those skilled in the art, this type of “source” termination allows for differential signals (e.g., clock signals) to pass through connectors that can be unplugged while the circuit is active, which is a type of “hot swapping.” As further shown by FIGS. 1A-1B, traditional HCSL drivers typically need to include a pair of 33Ω series resistors (RS) to inhibit signal reflection and ringing between the driver and the 50Ω PCB termination traces.
Referring now to FIG. 2, a conventional HCSL driver 20 is typically provided within a packaged integrated circuit device 22 having a plurality of external pins (e.g., P1, P2). As shown, the HCSL driver 20 includes a differential pre-driver 23, which generates a pair of differential output signals in response to a pair of differential input signals IN and /IN, and a differential main driver containing differential PMOS input transistors (M1, M2), which steer a bias current provided by a PMOS pull-up transistor M0 to off-chip loading resistors R1-R4, where R1-R2 (i.e., RT) are typically matched at 50Ω and R3-R4 (i.e., RS) are typically matched at 33Ω. As will be understood by those skilled in the art, a pair of resistors R5/R6 operate to sense the common-mode level of the two external pins P1, P2 and feed this common-mode level to a positive input port of an operational amplifier 25. This common-mode level is compared with a reference voltage (Vref), which is typically generated by a bandgap reference circuit (not shown), and the result of the comparison (at the output of the operational amplifier) is provided as a bias control signal to a gate terminal of the PMOS pull-up transistor M0. Based on this configuration, the operational amplifier operates within a negative feedback loop to regulate the common-mode level to the level of Vref.